已发表的文章
Towards Developing High Performance RISC-V Processors Using Agile Methodology
发表于 the 55th IEEE/ACM International Symposium on Microarchitecture (MICRO 2022). DOI: 10.1109/MICRO56248.2022.00080.
Our paper introduces XiangShan and the practice of agile development methodology on high performance RISC-V processors. It covers some representative tools we have developed and used to accelerate the chip development process, including design, functional verification, debugging, performance validation, etc. This paper is awarded all three available badges for artifacts evaluation.
This paper has been selected as an IEEE Micro Top Pick from the 2022 Computer Architecture Conferences. The updated article is published at IEEE Micro's annual special issue in July/August 2023. DOI: 10.1109/MM.2023.3273562.
Paper PDF | IEEE Xplore | BibTeX | Presentation Slides | Presentation Video | IEEE Micro Top Pick
香山开源高性能RISC-V处理器设计与实现
发表于计算机研究与发展, 2023, 60(3): 476-493. DOI: 10.7544/issn1000-1239.202221036.
Paper PDF | J-CRAD Online | 报告视频 | Research Highlight (in Chinese) By Jianlin Gao
Created: March 28, 2023